Please note: This article is based on the original paper presented at the symposium. It will be summarized at a high level for less technical readers and then also include some more technical details for readers who prefer them.<\/p>\n
\u00a0<\/h3>\nA closer look at the original testing method <\/strong><\/h3>\nThe longtime industry standard for predicting the lifetime of electronic devices has been a high-temperature-accelerated methodology using the Arrhenius equation. But what does that mean?<\/p>\n
\u201cHigh-temperature-accelerated\u201d<\/strong> means that instead of testing a device\u2019s lifetime by allowing it to age normally, researchers have found a way to accelerate the device\u2019s rate of aging by subjecting it to temperatures that are much higher than its standard operating temperature. That way, they can more rapidly detect failures or defects that might take years to appear under standard operating conditions.<\/p>\nThe Arrhenius equation<\/strong> represents the relationship between temperature and reaction rates and how temperature can accelerate those reactions.<\/p>\nFor NAND flash products<\/a>, lifetime is defined as how long it takes for the device to reach a predefined bit error rate at standard operating temperatures<\/a>.<\/p>\nFor those who prefer a more scientific take, here is a deeper explanation:<\/p>\n
The lifetime of a NAND flash product is defined as the retention time at device operation temperature (30o<\/sup>C to 40o<\/sup>C) when the bit error rate (BER) reaches a specific level, which is the upper limit of the error correction code (ECC) capability (see Figure 1). <\/em><\/p>\n![\"\"](\"https:\/\/phisonblog.com\/wp-content\/uploads\/2023\/09\/1680421_BlogGfxIRPSBlog_01_072623.jpg\")
<\/em><\/p>\nAccording to JEDEC documents, the lifetime in electronic devices can be estimated by temperature-accelerated methodology using the Arrhenius equation, which is:<\/em><\/p>\n <\/p>\n
<\/p>\n
![\"\"](\"https:\/\/phisonblog.com\/wp-content\/uploads\/2023\/10\/formula-1-300x62.jpg\")
<\/p>\n
<\/p>\n
<\/p>\n
In the equation, T1<\/sub> and T2<\/sub> are the bake temperature and device operation temperature, respectively. t1<\/sub> and t2<\/sub> are the retention time at T1<\/sub> and T2<\/sub>, respectively. k is Boltzmann\u2019s constant. Ea<\/sub> is the activation energy and represents the strength of temperature effect on data retention characteristics. Note that larger Ea<\/sub> (larger slope) represents the retention time has stronger temperature effect. In this model, it is assumed that Ea<\/sub> is a constant value and independent of bake temperature. Since Ea<\/sub> is a known factor, which is usually provided by the NAND vendor, the device lifetime t2<\/sub> at device operation temperature T2<\/sub> could be calculated accordingly by detecting the memory failure time t1<\/sub> at bake temperature T1<\/sub> (see Figure 2).<\/em><\/p>\n![\"\"](\"https:\/\/phisonblog.com\/wp-content\/uploads\/2023\/09\/1680421_BlogGfxIRPSBlog_02_072623.jpg\")
<\/em><\/p>\n <\/p>\n
What Phison found<\/h3>\n
In their research, Phison engineers discovered that one of the factors in the Arrhenius equation\u2014which had been assumed to be a constant unchanging value\u2014could actually vary in 3D NAND flash devices depending on baking temperature. That\u2019s because the scaling of cell size, the distance between cells and the tunneling layer in 3D NAND flash works differently than those factors in 2D NAND flash. This variance inevitably led to a gross overestimation of the device\u2019s lifetime.<\/p>\n
Technical details:<\/strong><\/p>\nIn Phison\u2019s recent study, it was discovered that Ea<\/sub> may not remain unchanged and would vary with baking temperature in 3D NAND flash (see Figure 3). <\/em><\/p>\n![\"\"](\"https:\/\/phisonblog.com\/wp-content\/uploads\/2023\/09\/1680421_BlogGfxIRPSBlog_03_072623.jpg\")
<\/em><\/p>\n <\/p>\n
t is clearly defined as a retention time when the BER arrives at a certain value. In the experiment, various <\/em>t was recorded in a wide range of baking temperature to extract Ea<\/sub>. The measured <\/em>t did not follow the conventional Arrhenius model (did not fall into a straight line), and exhibited two-stage behavior. Higher Ea<\/sub> is observed at T > 85o<\/sup>C, while lower Ea<\/sub> is extracted at T < 85o<\/sup>C. Since the evaluated device lifetime through the current qualification method is normally extracted by extrapolating from data points at higher temperature region to operation temperature region, the abnormal two-stage phenomenon would lead to a significant overestimation of retention lifetime.<\/em><\/p>\nIn general, the value of activation energy Ea<\/sub> is determined by physical mechanism. As a result, the aforementioned two-stage characteristics indicate that the retention failure is caused by more than one physical mechanism. <\/em><\/p>\nIn Phison\u2019s research, <\/em>the corresponding physical mechanisms at various retention temperatures and program\/erase (P\/E) cycle conditions in 3D NAND are validated experimentally for the first time. It has been proven that the peculiar two-stage feature is related to three different physical mechanisms (see Figures 4 and 5). <\/em><\/p>\n![\"\"](\"https:\/\/phisonblog.com\/wp-content\/uploads\/2023\/09\/1680421_BlogGfxIRPSBlog_04_072623.jpg\")
<\/em><\/p>\n![\"\"](\"https:\/\/phisonblog.com\/wp-content\/uploads\/2023\/09\/1680421_BlogGfxIRPSBlog_05_072623.jpg\")
<\/p>\n
At lower temperatures, the increment of BER tends to be dominated by silicon nitride (SiN)-trapped electron vertical loss through a direct tunneling (DT) process. At higher temperatures, the major physical mechanism depends on the P\/E cycle condition. The increment of BER in low P\/E-cycled devices is originated from SiN-trapped electron lateral migration via thermally-assisted tunneling (ThAT) while that in high P\/E-cycled devices is mainly caused by SiN-trapped electron vertical loss through Frenkel-Poole (F-P) emission, followed by the subsequent positive charge-assisted tunneling (PCAT) process.<\/em><\/p>\n\u00a0<\/h3>\nFindings lead to new (and more accurate) lifetime qualification methods<\/h3>\n
Thanks to the Phison team\u2019s research, the inaccuracy of 3D NAND flash lifetime testing was uncovered and explained to the industry at large. In order to resolve the issues of that inaccuracy, the team designed and presented two new testing methods that are now being used in Phison\u2019s reliability qualification process.<\/p>\n
\u00a0<\/h4>\nMultiple-activation-energies qualification method<\/h4>\n
This method includes a range of activation energies (that constant that turned out to not be so constant) at different temperatures to get a more accurate lifetime prediction.<\/p>\n
Technical details:<\/strong><\/p>\nIn the first step of this testing method, retention characteristics in a wide range of baking temperatures should be implemented to extract multiple Ea<\/sub> values. To simplify for explanation, we assume that only two different activation energies Ea, HT<\/sub> and Ea, LT<\/sub> are obtained (See Figure 6). <\/em><\/p>\n![\"\"](\"https:\/\/phisonblog.com\/wp-content\/uploads\/2023\/09\/1680421_BlogGfxIRPSBlog_06_072623.jpg\")
<\/em><\/p>\nIn the next step, device retention time t2<\/sub> at lower bake temperature T2<\/sub> could be calculated by measuring the memory failure time t1<\/sub> at higher bake temperature T1<\/sub>, as shown in this equation:<\/em><\/p>\n <\/p>\n
<\/p>\n
![\"\"](\"https:\/\/phisonblog.com\/wp-content\/uploads\/2023\/10\/formula-2-300x56.jpg\")
<\/p>\n
<\/p>\n
<\/p>\n
Finally, once t2<\/sub> is obtained, device lifetime t3<\/sub> at device operation temperature T3<\/sub> could be calculated with this equation:<\/em><\/p>\n <\/p>\n
<\/p>\n
![\"\"](\"https:\/\/phisonblog.com\/wp-content\/uploads\/2023\/10\/Formula-3-1-300x54.jpg\")
<\/p>\n
\u00a0<\/h4>\n\u00a0<\/h4>\n\u00a0<\/h4>\n\u00a0<\/h4>\nRoom-temperature-extrapolation qualification method<\/h4>\n
This method works by measuring the bit error rate of the device continuously during operation at room temperature. After multiple data points are collected, researchers can predict the device lifetime using a linear extrapolation.<\/p>\n
Technical details:<\/strong><\/p>\n![\"\"](\"https:\/\/phisonblog.com\/wp-content\/uploads\/2023\/09\/1680421_BlogGfxIRPSBlog_07_072623.jpg\")
<\/p>\n
.<\/em><\/p>\n <\/p>\n
Why Phison\u2019s research and recommendations matter<\/h3>\n
When manufacturers and consumers buy NAND flash or SSDs that contain the NAND flash modules, it\u2019s important to know how long those devices will last. The more accurate and transparent a NAND flash vendor can be about its products, the more its customers can rely on the brand. Thanks to Phison researchers<\/a>, the lifetime estimates of 3D NAND flash devices and modules will be more accurate\u2014which can help reduce unexpected downtime and other interruptions due to device failure.<\/p>\nPhison is dedicated to continuing research into electronics technology and advanced capabilities<\/a> to enable and support the applications and use cases of the future.<\/p>\n <\/p>\n
The longtime industry standard for predicting the lifetime of electronic devices has been a high-temperature-accelerated methodology using the Arrhenius equation. But what does that mean?<\/p>\n
\u201cHigh-temperature-accelerated\u201d<\/strong> means that instead of testing a device\u2019s lifetime by allowing it to age normally, researchers have found a way to accelerate the device\u2019s rate of aging by subjecting it to temperatures that are much higher than its standard operating temperature. That way, they can more rapidly detect failures or defects that might take years to appear under standard operating conditions.<\/p>\n The Arrhenius equation<\/strong> represents the relationship between temperature and reaction rates and how temperature can accelerate those reactions.<\/p>\n For NAND flash products<\/a>, lifetime is defined as how long it takes for the device to reach a predefined bit error rate at standard operating temperatures<\/a>.<\/p>\n For those who prefer a more scientific take, here is a deeper explanation:<\/p>\n The lifetime of a NAND flash product is defined as the retention time at device operation temperature (30o<\/sup>C to 40o<\/sup>C) when the bit error rate (BER) reaches a specific level, which is the upper limit of the error correction code (ECC) capability (see Figure 1). <\/em><\/p>\n According to JEDEC documents, the lifetime in electronic devices can be estimated by temperature-accelerated methodology using the Arrhenius equation, which is:<\/em><\/p>\n <\/p>\n <\/p>\n <\/p>\n <\/p>\n In the equation, T1<\/sub> and T2<\/sub> are the bake temperature and device operation temperature, respectively. t1<\/sub> and t2<\/sub> are the retention time at T1<\/sub> and T2<\/sub>, respectively. k is Boltzmann\u2019s constant. Ea<\/sub> is the activation energy and represents the strength of temperature effect on data retention characteristics. Note that larger Ea<\/sub> (larger slope) represents the retention time has stronger temperature effect. In this model, it is assumed that Ea<\/sub> is a constant value and independent of bake temperature. Since Ea<\/sub> is a known factor, which is usually provided by the NAND vendor, the device lifetime t2<\/sub> at device operation temperature T2<\/sub> could be calculated accordingly by detecting the memory failure time t1<\/sub> at bake temperature T1<\/sub> (see Figure 2).<\/em><\/p>\n <\/p>\n In their research, Phison engineers discovered that one of the factors in the Arrhenius equation\u2014which had been assumed to be a constant unchanging value\u2014could actually vary in 3D NAND flash devices depending on baking temperature. That\u2019s because the scaling of cell size, the distance between cells and the tunneling layer in 3D NAND flash works differently than those factors in 2D NAND flash. This variance inevitably led to a gross overestimation of the device\u2019s lifetime.<\/p>\n Technical details:<\/strong><\/p>\n In Phison\u2019s recent study, it was discovered that Ea<\/sub> may not remain unchanged and would vary with baking temperature in 3D NAND flash (see Figure 3). <\/em><\/p>\n <\/p>\n t is clearly defined as a retention time when the BER arrives at a certain value. In the experiment, various <\/em>t was recorded in a wide range of baking temperature to extract Ea<\/sub>. The measured <\/em>t did not follow the conventional Arrhenius model (did not fall into a straight line), and exhibited two-stage behavior. Higher Ea<\/sub> is observed at T > 85o<\/sup>C, while lower Ea<\/sub> is extracted at T < 85o<\/sup>C. Since the evaluated device lifetime through the current qualification method is normally extracted by extrapolating from data points at higher temperature region to operation temperature region, the abnormal two-stage phenomenon would lead to a significant overestimation of retention lifetime.<\/em><\/p>\n In general, the value of activation energy Ea<\/sub> is determined by physical mechanism. As a result, the aforementioned two-stage characteristics indicate that the retention failure is caused by more than one physical mechanism. <\/em><\/p>\n In Phison\u2019s research, <\/em>the corresponding physical mechanisms at various retention temperatures and program\/erase (P\/E) cycle conditions in 3D NAND are validated experimentally for the first time. It has been proven that the peculiar two-stage feature is related to three different physical mechanisms (see Figures 4 and 5). <\/em><\/p>\n At lower temperatures, the increment of BER tends to be dominated by silicon nitride (SiN)-trapped electron vertical loss through a direct tunneling (DT) process. At higher temperatures, the major physical mechanism depends on the P\/E cycle condition. The increment of BER in low P\/E-cycled devices is originated from SiN-trapped electron lateral migration via thermally-assisted tunneling (ThAT) while that in high P\/E-cycled devices is mainly caused by SiN-trapped electron vertical loss through Frenkel-Poole (F-P) emission, followed by the subsequent positive charge-assisted tunneling (PCAT) process.<\/em><\/p>\n Thanks to the Phison team\u2019s research, the inaccuracy of 3D NAND flash lifetime testing was uncovered and explained to the industry at large. In order to resolve the issues of that inaccuracy, the team designed and presented two new testing methods that are now being used in Phison\u2019s reliability qualification process.<\/p>\n This method includes a range of activation energies (that constant that turned out to not be so constant) at different temperatures to get a more accurate lifetime prediction.<\/p>\n Technical details:<\/strong><\/p>\n In the first step of this testing method, retention characteristics in a wide range of baking temperatures should be implemented to extract multiple Ea<\/sub> values. To simplify for explanation, we assume that only two different activation energies Ea, HT<\/sub> and Ea, LT<\/sub> are obtained (See Figure 6). <\/em><\/p>\n In the next step, device retention time t2<\/sub> at lower bake temperature T2<\/sub> could be calculated by measuring the memory failure time t1<\/sub> at higher bake temperature T1<\/sub>, as shown in this equation:<\/em><\/p>\n <\/p>\n <\/p>\n <\/p>\n <\/p>\n Finally, once t2<\/sub> is obtained, device lifetime t3<\/sub> at device operation temperature T3<\/sub> could be calculated with this equation:<\/em><\/p>\n <\/p>\n <\/p>\n This method works by measuring the bit error rate of the device continuously during operation at room temperature. After multiple data points are collected, researchers can predict the device lifetime using a linear extrapolation.<\/p>\n Technical details:<\/strong><\/p>\n .<\/em><\/p>\n <\/p>\n When manufacturers and consumers buy NAND flash or SSDs that contain the NAND flash modules, it\u2019s important to know how long those devices will last. The more accurate and transparent a NAND flash vendor can be about its products, the more its customers can rely on the brand. Thanks to Phison researchers<\/a>, the lifetime estimates of 3D NAND flash devices and modules will be more accurate\u2014which can help reduce unexpected downtime and other interruptions due to device failure.<\/p>\n Phison is dedicated to continuing research into electronics technology and advanced capabilities<\/a> to enable and support the applications and use cases of the future.<\/p>\n <\/p>\n<\/em><\/p>\n<\/p>\n<\/em><\/p>\nWhat Phison found<\/h3>\n
<\/em><\/p>\n<\/em><\/p>\n<\/p>\n\u00a0<\/h3>\n
Findings lead to new (and more accurate) lifetime qualification methods<\/h3>\n
\u00a0<\/h4>\n
Multiple-activation-energies qualification method<\/h4>\n
<\/em><\/p>\n<\/p>\n<\/p>\n\u00a0<\/h4>\n
\u00a0<\/h4>\n
\u00a0<\/h4>\n
\u00a0<\/h4>\n
Room-temperature-extrapolation qualification method<\/h4>\n
<\/p>\nWhy Phison\u2019s research and recommendations matter<\/h3>\n
![\"\"](\"https:\/\/phisonblog.com\/wp-content\/uploads\/2023\/03\/Phison-New-Imagin-Custom-Platform.jpg\")