In the age of intelligence, high-speed and highly reliable storage solutions are essential in a wide range of domains including factory automation, automotive, farming, 5G networks and space applications. These environments require rapid processing of large data volumes while also ensuring system stability for extended periods of continuous operation.
As a global storage solutions leader, Phison has over 20 years of experience delivering advanced embedded and industrial solutions. Using a combination of pseudo single-level-cell (pSLC) technology, advanced error correction code (ECC) and Machine Learning (ML), Phison’s storage products are the optimal choice for flash storage applications that must operate in extreme environments. Whether it’s on the ground, at sea, in the air or up in space, customers can rely on Phison’s storage solutions.
Pseudo SLC mode
All modern NAND cells can operate in pSLC mode. This capability has existed since early multilevel cell (MLC) first came on the market in 2009. Though the pSLC capability is rarely used in typical client or enterprise applications, it is of great use to industrial, medical, automotive, aviation and space write-intensive use cases. Phison has provided pSLC solutions to these markets for well over a decade.
Cells used in pSLC mode have the same programming speed and endurance as dedicated SLC, but benefit from modern smaller cell sizes and 3D configurations, which reduce overall cost. One question that comes up frequently is whether pseudo MLC (pMLC) mode could work as a middle ground for those who need a bit more capacity. Unfortunately, the physics behind NAND cells don’t currently support that option.
NAND cells are a bit like buckets that hold water, but in this case the water is a pile of electrons. With pSLC, the bucket is either empty or not empty. As soon as you add levels of not-emptiness (or more bits), the number of electrons, or voltage level, must be controlled much more precisely. This means the cell-filling process takes longer, which causes more stress on the physical hardware and shortens the life of the cell. Where a pSLC cell can write quickly and lasts up to 100,000 cycles, a triple-level cell (TLC) is limited to 3,000 cycles. Quad-level cells (QLC) max out at about 1,200. Should penta-level cells (PLC) with 5 bits ever be commercialized, they will likely have less than 600 cycles, severely limiting their usefulness.
As things stand today, both TLC and QLC can support pSLC mode. This option is a significantly less expensive alternative to traditional SLC. It also provides enhanced performance and endurance over the normal 3D NAND cell. Though the cycling capability of SLC is helpful, it is not sufficient to build a high-endurance product. At Phison our first priority is ensuring the user data is safe across a wide range of demanding environments. This is where advanced ECC comes in.
Advanced Error Correction Code (ECC) technology
With over 20 years of experience in the NAND flash industry, Phison has developed sophisticated Error Correction Code (ECC) technology. The current state of the art is based on the low-density parity check (LDPC) ECC algorithm. It is a very efficient statistical model built using millions of hours of testing. Though not quite based on machine learning (ML), it is close—and much more efficient than the previous Bose-
Chaudhuri-Hocquenghem (BCH) algorithmic model. Phison’s fourth generation LDPC engine can be found in all the company’s latest controllers. We’ve also started work on our next LDPC engine to ensure continuous improvement of our products.
But why does data go bad on NAND modules in the first place? Both heat and high-speed particles (protons and neutrons from the sun) cause an increase in the overall energy of the cell. These atomic particle strikes happen all the time, even at sea level, and have a real effect on electronics. Conversely, electrons leak out of NAND cells over time, which causes energy levels to go down. These variations in cell charge are not uniform. This is where ECC comes in to help the SSD figure out what the data is supposed to be.
Reliability enhancement: Machine-learning-based error recovery flow
While LDPC is not based on ML techniques, it can be improved with ML. Phison has enhanced product performance, retention and reliability even further through the use of detailed NAND channel modeling. The technology is divided into two parts: hard decoder and soft decoder.
New generation of hard decoder: Robust read-level search algorithm with Coarse Tune and Fine Tune steps
The hard decoder is so named because it uses the direct information provided by the ECC bits appended to the data. By changing the way the NAND cells are read, the hard decoder algorithm can often correct data with one or two attempts. The trick to getting good efficiency is knowing which of the 20+ read modes should be used and when. By using a selection method based on ML, recovery latency can be greatly reduced.
Another technique used to coax more information out of the cells involves skewing the selection thresholds to determine whether a borderline voltage level represents value A or value B. While it is certainly possible to iterate through every permutation of read retry and voltage thresholds, an ML algorithm can perform the recovery much more efficiently by skipping steps that it knows are not effective for the current conditions. In such cases, the key to reliability and latency is an accurate and efficient algorithm to search for the optimal read level.
Phison has developed a robust ML algorithm with two stages called Coarse Tune and Fine Tune. The Coarse Tune phase takes a maximum of three reads to dynamically identify the current optimal read level—with better convergence speed and more
accurate prediction results than other solutions. The Fine Tune phase builds on the prior results to finesse the remaining parameters. Once the correct settings are identified, they can typically be used for the other data pages on the NAND.
New generation of soft decoder: ML-based prediction model with Auto-Calibrated LLR
The soft decoder is used when the NAND data is too damaged to read with hard decoder techniques. In this mode, extra decode information is obtained using all three TLC pages (or four pages for QLC) from the cells in a given page. Other interpolation modes allow sampling from physically adjacent pages. Though slower, this mode gives more information to the decoder so that it can better determine how to correct the data. At this point, speed is no longer a concern as the data is considered lost unless the soft decoder can fix the corruption. Another term for this mode that correctly frames the priority is “heroic error recovery.”
For soft decoder, the goal is to maximize the decoding capability to recover the original data. Given a specified channel model and optimal soft read offset, an optimal log-likelihood ratio (LLR) value can be calculated.
Phison’s ML-based prediction model for the optimal LLR value is called Auto-Calibrated LLR (ACLLR). The optimal LLR prediction can be considered as a regression,
classification or clustering problem in machine learning. Test results have shown that Phison’s ACLLR has better decoding capability than standard LLR.
Phison’s strong research and development capabilities featuring pSLC, advanced ECC and ML algorithms deliver outstanding performance and reliability. The company’s solutions are an ideal choice for tough environments and demanding workloads. With exceptional quality and high performance, Phison’s storage solutions are an ideal choice for businesses seeking a competitive edge in today’s fast-paced digital landscape.
Phison’s ultra-reliable storage portfolio offers a wide range of industrial grade form factors including solder-down BGA, along with conventional 2.5″, M.2 2280, M.2 2242 and more:
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- SATAIII (MST360 series with Phison controller PS3117-S17TI
- PCIe Gen3 (MPT160 series with Phison controller PS5013-E13TI
- PCIe Gen4 (MPD660 series with Phison controller PS5018-E18DI
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